In a typical replacement gate process for manufacturing a FET, a dummy gate is lithographically formed on the substrate, spacers are formed on the sidewalls of the dummy gate, and a dielectric is deposited to cover the gates and fill the areas between gates. The dielectric is then polished or etched back so as to be co-planar with the dummy gate. Then the dummy gate is removed leaving an opening in the dielectric. Within the opening, a gate dielectric is deposited and the remainder of the opening is over-filled with gate material. The structure is then polished so that the gate material in the opening and the dielectric are co-planar. In a typical replacement gate process, the height of the opening, and thus, the opening's aspect ratio, is determined by the dummy gate dimensions. In a typical replacement gate process, voids commonly form in the gate. Voids in the gate are detrimental to device performance.